1. Field of the Invention
The present invention relates to a clock supply control apparatus and method that controls the supply of clocks to PCI devices of a computer system.
2. Description of the Related Art
Recently, there is the demand for saving the power consumption of computer systems. A computer system that is configured to have the clock run function in order to for the saving of the power consumption of PCI (peripheral component interconnect) devices is known.
The clock run function is aimed at saving the power consumption of PCI devices connected to a PCI bus within the computer system. A clock run signal line connects a power management controller and the PCI devices, and a clock run signal is delivered on the signal line to such PCI devices. When the clock run signal line is asserted, the supply of clocks to the PCI devices is allowed. When the clock run signal line is not asserted, the supply of clocks to the PCI devices is inhibited. At this time, the PCI devices stop operations in the absence of the clocks supplied, thereby achieving the power consumption saving.
Generally, a PCMCIA (Personal Computer Memory Card International Association) controller, which is provided as one of the PCI devices in a personal computer system, is configured to have an interrupt processing function in order to allow a known plug-and-play capability of a PC card. However, if the supply of a PCI bus clock to the PCMCIA controller is inhibited by performing the clock run function, the interrupt processing function of the PCMCIA controller is placed in the inactive condition because of the absence of the clock supplied thereto. Hence, there is a problem in that the PCMCIA controller in such a condition is unable to provide the plug-and-play capability of the PC card. To avoid the problem, in a conventional computer system in which the PCMCIA controller is installed, the clock run function is set in the inactive condition in order to allow the plug-and-play capability of the PC card. In the conventional computer system, the clock run function cannot suitably be used at the same time as the time the interrupt processing function of the PCMCIA controller is active.
It is desirable to provide a clock supply control mechanism that allows the PCMCIA controller to suitably use the clock run function to provide the saving of the consumption power when the interrupt processing function of the PCMCIA controller is active.
In order to facilitate understanding of the above problems, FIG. 1 is a diagram for explaining the clock run function which is performed in a personal computer system.
As shown in FIG. 1, a computer system 1 includes a bus controller 11 and a power management controller 12. A PCI bus 2 connects the bus controller 11 with a plurality of devices 5-1 through 5-n. A signal line 3 connects the power management controller 12 with the plurality of devices 5-1 through 5-n. The power management controller 12 is connected to an oscillator circuit 4. The oscillator circuit 4 generates a clock having a given frequency, and delivers the clock to each of the devices 5-1 through 5-n. The power management controller 12 controls the supply of the clock to the devices 5-1 through the 5-n. 
In the computer system 1 of FIG. 1, the power management controller 12 provides the clock run function for the devices 5-1 through 5-n connected to the signal line 3, as follows.
The power management controller 12 detects whether the signal line 3 on which a clock run signal is sent is asserted high. When the signal line 3 is active-high, the power management controller 12 controls the oscillator circuit 4 so that the supply of the clock from the oscillator circuit 4 to each of the devices 5-1 through 5-n is inhibited. At this time, the devices 5-1 through 5-n do not operate because of the absence of the clock supplied thereto, and they do not excessively consume the power. Namely, the clock run function, provided by the power management controller 12, is active for saving the power consumption of the devices 5-1 through 5-n. 
When the signal line 3 is inactive or low, the power management controller 12 controls the oscillator circuit 4 so that the supply of the clock from the oscillator circuit 4 to each of the devices 5-1 through 5-n is allowed. At this time, the devices 5-1 through 5-n are normally operating in accordance with the clock supplied. Namely, the clock run function, provided by the power management controller 12, is inactive for saving the power consumption of the devices 5-1 through 5-n. 
As described above, the PCMCIA controller as one of the PCI devices is configured to have an interrupt processing function in order to achieve a plug-and-play capability of a PC card. Specifically, in the PCMCIA controller, when the PC card is inserted into the computer, the insertion of the PC card causes the interrupt processing function of the PCMCIA controller to be performed to notify the computer of the presence of the inserted PC card. The computer recognizes the PC card through the interrupt processing function of the PCMCAI controller, and the plug-and-play capability of the PC card is thus achieved.
FIG. 2 is a diagram for explaining an interrupt processing process of the PCI devices in a computer system. In FIG. 2, the elements which are essentially the same as corresponding elements in FIG. 1 are designated by the same reference numerals, and a description thereof will be omitted.
As shown in FIG. 2, a plurality of interrupt (INT) signal lines 21-1 through 21-n connect the plurality of the PCI devices 5-1 through 5-n with the bus controller 11. The PCI bus 2 connects the bus controller 11 with the PCI devices 5-1 through 5-n. 
In the computer system of FIG. 2, the bus controller 11 detects whether one of the INT signal lines 21-1 through 21-n on which an interrupt signal is sent is asserted high. Hereinafter, one of the INT signal lines 21-1 through 21-n is indicated by reference numeral “21-i”. When the INT signal line 21-i is active-high, the bus controller 11 determines that an interrupt request is issued from the PCI device connected to the INT signal line 21-i. Hereinafter, the PCI device connected to the INT signal line 21-i is indicated by reference numeral “5-i”. The bus controller 11 delivers the interrupt signal, issued from the PCI device 5-i, to the computer. The operating system of the computer temporarily stops what it is doing to divert its attention to the service required by the interrupt signal.
The configuration of the computer system shown in FIG. 2 requires the “n” interrupt signal lines 21-1 through 21-n, which will increase the number of wires and the number of input/output terminals, related to the bus controller 11, on the integrated circuit chip. With the configuration of FIG. 2 used, there is a difficulty in providing a small-size clock supply control apparatus.
FIG. 3 is a diagram for explaining a serialized interrupt processing process of the PCI devices in a computer system. In FIG. 3, the elements which are essentially the same as corresponding elements in FIG. 1 are designated by the same reference numerals, and a description thereof will be omitted.
In order to eliminate the problem of the configuration of FIG. 2, in the configuration of the computer system shown in FIG. 3, an interrupt signal line 32 is shared by a plurality of PCI devices 31-1 through 31-n, and a serialized interrupt processing process is performed in the computer system.
As shown in FIG. 3, the common interrupt signal line 32 connects the PCI devices 31-1 through 31-n with a bus controller 33. The PCI bus 2 connects the bus controller 33 with the PCI devices 31-1 through 31-n. A specific pattern of interrupt signals allocated for the PCI devices 31-1 through 31-n is predetermined. When an interrupt request is issued from one of the PCI devices 31-1 through 31-n, the specific pattern in which a corresponding interrupt signal sent from the PCI device 31-i is set is sent to the bus controller 33 on the interrupt signal line 32 at a given timing.
In the computer system of FIG. 3, the bus controller 33 receives the specific pattern, including the interrupt signal, from the interrupt signal line 32 at the given timing, and recognizes that the interrupt request is issued from a particular one of the PCI devices (or the PCI device 31-i) based on the received pattern. In this configuration, the PCI devices 31-1 through 31-n must generate the interrupt signals of the specific pattern in accordance with the PCI bus clock supplied thereto, and control the timing that they output the interrupt signals of the specific pattern to the interrupt signal line 32.
The configuration of the computer system shown in FIG. 3 requires that the PCI devices 31-1 through 31-n output the interrupt signals of the specific pattern to the interrupt signal line 32 at the given timing. To meet the requirement, the PCI devices 31-1 through 31-n must be operated in synchronism with the PCI bus clock supplied thereto.
However, in the configuration of FIG. 3, if the supply of the PCI bus clock to the PCI devices 31-1 through 31-n is inhibited by performing the clock run function, the interrupt processing function of the PCI devices 31-1 through 31-n is placed in the inactive condition because of the absence of the clock supplied thereto. Hence, there is a problem in that the PCMCIA controller in the inactive condition is unable to provide the plug-and-play capability of the PC card through the interrupt processing function. To avoid the problem, in the conventional computer system in which the PCMCIA controller is installed, the clock run function is set in the inactive condition in order to allow the plug-and-play capability of the PC card. In the conventional computer system, the clock run function cannot suitably be used at the same time as the time the interrupt processing function of the PCMCIA controller is active.